Regviz

NXP Semiconductors /LPC43xx /CCU1 /CLK_M4_ETHERNET_STAT

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLK_M4_ETHERNET_STAT

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC43xx/CCU1/CLK_M4_ETHERNET_STAT#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RUN)RUN 0 (AUTO)AUTO 0 (WAKEUP)WAKEUP 0RESERVED

Description

CLK_M4_ETHERNET clock status register

Fields

RUN

Run enable status 0 = clock is disabled. 1 = clock is enabled.
AUTO

Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled.
WAKEUP

Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled.
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data